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LCD01D |
The LCD01D is a high speed decoder for the DVB-S2/DVB-S2X low density parity check (LDPC) and Bose, Chaudhuri and Hocquenghem (BCH) code standard.
Features
- Digital Video Broadcasting Second Generation (DVB-S2) and Extensions
(DVB-S2X) compatible
- Nominal code rates from 1/5 to 9/10
- Data lengths from 2512 to 58192 bits
- Optional π/2 BPSK SF2, π/2 BPSK, QPSK, 8PSK, 8APSK, 16APSK, 32APSK,
64APSK, 128APSK and 256APSK demapping and deinterleaving with 11-bit
inphase and quadrature two's complement input
- Optional interleaved or deinterleaved 8-bit log-likelihood-ratio (LLR)
input
- Includes ping-pong input and output memories, BCH decoder and optional
descrambler
- Up to 323 MHz internal clock
- Up to 290 Mbit/s with 30 decoder iterations
- Up to 256 iterations
- Programmable signal points
- Scaled min-sum modified Gauss-Seidel LDPC decoding algorithm
- Optional power efficient early stopping
- LDPC parity check and BCH error location polynomial degree output
- ~42,000 LUTs and 287 RAMB18s for Xilinx Virtex-5, Virtex-6, 7-Series,
UltraScale and UltraScale+ FPGAs. ~53,000 ALUTs and 436 M10Ks for Altera
Cyclone V.
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Available as VHDL core for Xilinx
FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and
Microsemi/Actel cores available on request.
- Free
simulation software
- Data Sheet 1 Dec. 2021 (v1.04)
Specifications subject to change without notice.
Last update 1 Dec 2021. Home