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PCE04CH |
PCE04CH
This is a high speed 16 state CCSDS compatible parallel concatenated turbo
encoder with sync marker, optional pseudo-randomiser and input memory.
Features
- 16 state CCSDS compatible turbo encoder
- Rate 1/2, 1/3, 1/4 and 1/6
- Interleaver sizes from 1784 to 16056 bits in multiples of 1784
- Includes sync marker, optional pseudo-randomiser and ping-pong input
memory
- Up to 706 MHz internal clock
- Up to 346 Mbit/s encoding speed
- Serial continuous encoded data out
- 254 or 216 6-input LUTs with 1 or 2 18 kB RAMB18s
- Asynchronous logic free design
Available as EDIF and VHDL core for
Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and
Microsemi/Actel cores available on request.
- Data Sheet 4 Aug. 2023 (v1.03)
Specifications subject to change without notice.
Last update 4 Aug. 2023. Home