PCE03V

This is a high speed 8 state 3GPP^TM (UMTS and LTE) and 3GPP2 (1xEV-DV Release D and 1xEV-DO Release B) compatible parallel concatenated turbo encoder.

Features

• 8 state 3GPP^TM (UMTS and LTE) and 3GPP2 (1xEV-DV Release D and 1xEV-DO Release B) compatible turbo encoder
• Rate 1/2, 1/3, 1/4 or 1/5
• 40 to 5114 (3GPP^TM UMTS), 40 to 6144 (3GPP^TM LTE) or 17 to 32768 (3GPP2) bit interleaver
• Implement one, two or four different standards from the one core
• Up to 197 MHz internal clock
• Up to 98.5 Mbit/s encoding speed
• Serial continuous encoded data out
• Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6 and Spartan-6 FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
• Available as VHDL core for ASICs
• Low cost university license also available
• Data Sheet 26 November 2010 (v1.43)

Last update 26 Nov 2009. Home