PCD04C

This is a CCSDS compatible 16 state error control turbo decoder. The PCD04C offers unparalled speed, performance, low complexity and features compared to other available decoder cores.

Turbo Decoder

• 16 state CCSDS compatible
• Rate 1/2 to 1/7
• 1784 to 16056 bit interleaver
• Up to 130 MHz internal clock
• Up to 12.8 Mbit/s with 5 decoder iterations
• 6-bit signed magnitude input data
• Log-MAP or max-log-MAP constituent decoder algorithms
• Up to 128 iterations in 1/2 iteration steps
• Power efficient early stopping
• Extrinsic information output with optional scaling and limiting
• Full estimated channel error output
• Free simulation software

• 64 or 256 state (constraint length 7 or 9)
• Rate 1/2, 1/3 or 1/4
• Block lengths from 1784 to 16056 bits
• Up to 3.8 Mbit/s (256 state) or 12.9 Mbit/s (64 state)
• 6-bit signed magnitude input data
• Estimated channel error output

• Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6 and Spartan-6 FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
• Available as VHDL core for ASICs
• Low cost university license also available
• Data Sheet 9 June 2011 (v1.49)

Last update 9 Jun 2011. Home