PCD03V

This is a fully compatible 3GPP^TM (UMTS and LTE) and 3GPP2 (1xEV-DV Release D and 1xEV-DO Release B) error control decoder. The decoder can be used to decode the standard 3GPP^TM or 3GPP2 8 state turbo code and 16, 32, 64 or 256 state convolutional codes. The PCD03V offers unparalled speed, performance, low complexity and features compared to other available 3GPP^TM or 3GPP2 decoder cores.

Turbo Decoder

• 8 state 3GPP^TM (UMTS and LTE) and 3GPP2 (1xEV-DV Release D and 1xEV-DO Release B) compatible
• Rate 1/2, 1/3, 1/4 or 1/5
• 40 to 5114 (3GPP^TM UMTS), 40 to 6144 (3GPP^TM LTE) or 17 to 21504 (3GPP2) bit interleaver
• Optional external interleaver parameters for 3GPP^TM LTE and programmable row coefficients for 3GPP2 interleaver
• Up to 145 MHz internal clock
• Up to 13.8 Mbit/s with 5 decoder iterations
• 6-bit signed magnitude or two's complement input data
• Optional log-MAP or max-log-MAP constituent decoder algorithms
• Up to 128 iterations in 1/2 iteration steps
• Optional power efficient early stopping
• Optional extrinsic information scaling and limiting
• Estimated channel error output
• Implement one, two, three or four different standards from the one core
• Free simulation software

• 16, 32, 64 or 256 states (constraint lengths 5, 6, 7 or 9)
• Rate 1/2, 1/3 or 1/4
• Data lengths from 1 to 32768-m bits with tail termination of m bits (m is encoder memory)
• Optional tail biting decoding from 10 to 1928 data bits (short delay) or 20 to 1808 data bits (long delay)
• Up to 3.4 Mbit/s (256 state) or 11.5 Mbit/s (16, 32 or 64 states)
• 6-bit signed magnitude or two's complement input data
• Estimated channel error output

• Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6 and Spartan-6 FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
• Available as VHDL core for ASICs
• Low cost university license also available
• Data Sheet 10 Aug 2011 (v1.85)

Last update 10 Aug 2011. Home