PCD03L8

This is a very high speed and fully compatible 3GPP^TM LTE turbo decoder with eight parallel MAP decoders.

Features

• 8 state 3GPP^TM LTE compatible turbo decoder
• Rate 1/3
• 40 to 6144 bit interleaver
• Up to 185 MHz internal clock
• Up to 130 Mbit/s with 5 decoder iterations
• 6-bit signed magnitude input data
• 8 parallel MAP decoders
• Optional log-MAP or max-log-MAP constituent decoder algorithms
• Up to 32 iterations in 1/2 iteration steps
• Optional power efficient early stopping
• Optional extrinsic information scaling and limiting
• Estimated channel error output
• Free simulation software
• Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6 and Spartan 6 FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
• Available as VHDL core for ASICs
• Low cost university license also available
• Data Sheet 28 Dec 2010 (v1.03)

Last update 28 Dec 2010. Home