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PCD03D |
This is a fully compatible DVB-RCS and IEEE 802.16e error control decoder. The
decoder can be used to decode the standard 8 state duo-binary tail-biting
turbo code or 64 state convolutional code. The PCD03D offers unparalled speed, performance, low complexity and features compared to other available
DVB-RCS or IEEE 802.16e decoder cores.
Turbo Decoder
- 8 state DVB-RCS and IEEE 802.16e compatible
- Rate 1/3, 2/5, 1/2, 2/3, 3/4, 4/5, 5/6, 6/7, 7/8
- Automatic depuncturing
- 48 to 2048 or 5120 bit data length
- Up to 86 MHz internal clock
- Up to 15.7 Mbit/s with 5 decoder iterations (X times faster with X
parallel decoders)
- 6-bit signed magnitude input data
- Optional log-MAP or max-log-MAP constituent decoder algorithms
- Up to 128 iterations in 1/2 iteration steps
- Optional power efficient early stopping
- Optional extrinsic information scaling and limiting
- Estimated channel error output
- DVB-RCS or IEEE 802.16e implementation options
- Free
simulation software
Viterbi Decoder (Available Separately)
- 64 state (constraint length 7)
- Rate 1/2, 2/3, 3/4, 5/6, 7/8
- Automatic depuncturing
- Data length from 1 to 8186 bits
- Up to 8.4 Mbit/s
- 4-bit signed magnitude input data
- Estimated channel error output
Available as EDIF core and VHDL
simulation core for Xilinx Virtex-II Pro, Spartan-3 family and Virtex-4
FPGAs under SignOnce IP License
- Available as VHDL core for ASICs
- Low cost university license also available
- Data Sheet 21 Jun 2007 (v1.00)
Specifications subject to change without notice.
Last update 21 Jun 2007. Home