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PCD03D |
This is a fully compatible DVB-RCS and IEEE 802.16 WiMAX error control decoder.
The decoder can be used to decode the standard 8 state duo-binary tail-biting
turbo code or 64 state convolutional code. The PCD03D offers unparalleled speed, performance, low complexity and features compared to other available
DVB-RCS or IEEE 802.16 WiMAX decoder cores.
Turbo Decoder
- 8 state DVB-RCS and IEEE 802.16 WiMAX compatible
- Rate 1/3, 2/5, 1/2, 2/3, 3/4, 4/5, 5/6, 6/7, 7/8
- Automatic depuncturing
- 48 or 96 to 2048 or 5120 bit data length
- Up to 197 MHz internal clock
- Up to 35 Mbit/s with 5 decoder iterations
- 6-bit signed magnitude input data
- Optional log-MAP or max-log-MAP constituent decoder algorithms
- Up to 128 iterations in 1/2 iteration steps
- Optional power efficient early stopping
- Optional extrinsic information scaling and limiting
- Estimated channel error output
- Decoded symbol log probability output
- DVB-RCS or IEEE 802.16 WiMAX implementation options
- Free
simulation software
Viterbi Decoder (Optional)
- 64 state (constraint length 7)
- Rate 1/2, 2/3, 3/4, 5/6, 7/8
- Automatic depuncturing
- Data length from 2 to 2042 or 4090 bits with tail termination
- Optional tail biting decoding from 22 or 43 to 511 data bits
- Up to 19 Mbit/s
- 6-bit signed magnitude input data
- Estimated channel error output
Available as EDIF core and VHDL
simulation core for Xilinx FPGAs under SignOnce IP License. Actel, Altera
and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Data Sheet 3 Jun 2015 (v1.12)
Specifications subject to change without notice.
Last update 3 Jun 2015. Home